The auxiliary integrated circuit is made up of a series of specialized chips for audio, video and control applications . Formerly it was made up of more than a dozen small chips, but today its architecture has been profoundly simplified, with three well differentiated blocks: the north bridge, the south bridge and the connection between bridges.
The chip that makes up the north bridge is also known as the northbridge , Memory Controller Hub (MCH) or memory controller hub. It is responsible for controlling memory, PCI Express and the AGP bus , as well as serving as a data transmission interface with the South Bridge chip.
Modern Intel CPUs include PCI Express and memory control functions, so the north bridge is unnecessary. In AMD there is northbridge , but this only is in charge of controlling the AGP or PCI Express; memory controllers are integrated into the processor. Older chipsets have an even more inefficient architecture in which multiple buses are used to control the RAM and graphics card.
It is important to know the structure of the north bridge, the number of point-to-point lanes of the PCIe (x1, x4, x8, x16 and x32 are the usual ones) and the transfer speed of the connection before purchasing the chipset .
The PCI-SIG standard associates each denomination with a unique bandwidth makes it easy to know the specifications of the component. The first generation of PCI Express, PCIe 1.0 released in 2003, features data transfer speeds of 2.5 GT / s; the PCIe 5.0 released this year reaches 32 GT / s.
To choose a PCIe connector it is necessary to know what use it will be used for. The following list gives a general idea of the rails required by different hardware components :
1 lanes: network drivers, audio, USB connectors up to 3.1 Gen. 1.
2 lanes: USB 3.1 Gen. 2 and above, SSD drives.
4 lanes: firmware- based RAID controllers , Thunderbolt applications, M.2 expansion cards (old NGFF).
8 or 16 lanes: specialized PCIe cards, graphics cards.
The number of total lanes of the auxiliary integrated circuit or CPU is relevant when the number of connected components is expected to be high. Today’s high-end models have up to 128 lanes.
Returning to the general scheme of the chipset , another of the basic blocks that make it up is the south bridge. This is also known as southbridge , I / O Controller Hub (ICH), Platform Controller Hub (PCH), I / O controller hub, or platform controller hub.
The south bridge controls the input and output devices, as well as the integrated audio, network and image equipment . Below is the complete list of these elements:
Storage Ports (Sata And Parallel)
Integrated local area network
PCI Express lanes
RTC real time clock
CMOS or ROM memory: BIOS and Unified Extensible Firmware Interface (UEFI)
Super I / O chip (for controlling DMA, PS / 2 ports and other outdated technologies)
Finally, the north bridge and the south bridge are linked through a PCI connection known as an inter-bridge . If this element has a poor transfer speed, it will form a bottleneck in the auxiliary integrated circuit.
Each processor company presents its own solution. In Intel there is a dedicated connection known as Direct Media Interface or DMI, similar to a full-duplex PCIe . It achieves a bandwidth of 1 GB / s per direction, or 10 Gbps between the four point-to-point lanes that configure the DMI. AMD uses an information path known as A-Link with three versions: Basic, II, and III. These are PCIe 1.1 and 2.0 lanes (for A-Link III) with four lanes.